Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation

ISBN: 0-7695-2533-4International audienceDynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture process. We present a method which generates automatically the design for both partially and fixed parts of FPGAs

Speed-up run-time reconfiguration implementation on FPGAs

International audienceReconfigurable computing is certainly one of the most important emerging research topics over the last few years, in the field of digital processing architectures. The introduction of run-time reconfiguration (RTR) on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose we present an automatic design generation methodology for heterogeneous architectures based on Network on Chip (NoC) and FPGAs that eases and speed-up RTR implementation. We focus on how to take into account specificities of partially reconfigurable components during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of a FPGA with automaticmanagement of the reconfiguration process. Furthermore this automatic design generation enables reconfiguration pre-fetching techniques to minimize reconfiguration latency and buffer merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. The implementation example illustrates the benefits of the proposed design methodology

Design methodology for runtime reconfigurable FPGA: From high level specification down to implementation

In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where application is represented by a control data flow graph and architecture by an architecture graph. We focus on how to take into account specificities of partially reconfigurable components during the adequation process and for the design generation. We present a method which generates automatically the design for both fixed and partially reconfigurable parts of a FPGA. This method uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration and buffer merging to minimize memory requirements of the generated design

Impact of classic and paradoxical low flow on survival after aortic valve replacement for severe aortic stenosis

BackgroundLow flow (LF) can occur with reduced (classic) or preserved (paradoxical) left ventricular ejection fraction (LVEF). ObjectivesThe objective of this study was to compare outcomes of patients with low ejection fraction (LEF), paradoxical low flow (PLF), and normal flow (NF) after aortic valve replacement (AVR). MethodsWe examined 1,154 patients with severe aortic stenosis (AS) who underwent AVR with or without coronary artery bypass grafting. ResultsAmong these patients, 206 (18%) had LEF as defined by LVEF of 35 ml · m2. Aortic valve area was lower in low flow/LVEF groups (LEF: 0.71 ± 0.20 cm2 and PLF: 0.65 ± 0.23 cm2 vs. NF: 0.77 ± 0.18 cm2; p < 0.001). The 30-day mortality was higher (p < 0.001) in LEF and PLF groups than in the NF group (6.3% and 6.3% vs. 1.8%, respectively). SVi and PLF group were independent predictors of operative mortality (odds ratio [OR]: 1.18, p < 0.05; and OR: 2.97, p = 0.004; respectively). At 5 years after AVR, overall survival was 72 ± 4% in LEF group, 81 ± 2% in PLF group, and 85 ± 2% in NF group (p < 0.0001). ConclusionsPatients with LEF or PLF AS have a higher operative risk, but pre-operative risk score accounted only for LEF and lower LVEF. Patients with LEF had the worst survival outcome, whereas patients with PLF and normal flow had similar survival rates after AVR. As a major predictor of perioperative mortality, SVi should be integrated in AS patients’ pre-operative evaluation

A prototyping platform based on a PCI micronetwork and Leon multiprocessor system

System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunication, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers ability to conceive complex electronic engines under strong time to market pressure. Success relies on using appropriate design and process technologies, on the ability to interconnect existing components including processors, controllers, and memory array reliably as well as on the capability to validate such complex designs. This last point is the topic of this paper, which presents a prototyping methodology and flexible hardware platform developed to facilitate rapid prototyping and validation of such telecommunication systems

A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs

18 pagesInternational audienceReconfigurable computing is certainly one of the most important emerging research topics on digital processing architectures over the last few years. The introduction of run-time reconfiguration (RTR) on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose, we present an automatic design generation methodology for heterogeneous architectures based on DSPs and FPGAs that ease and speed RTR implementation. We focus on how to take into account specificities of partially reconfigurable components from a high-level specification during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of an FPGA with automatic management of the reconfiguration process. Furthermore, this automatic design generation enables a reconfiguration prefetching technique to minimize reconfiguration latency and buffer-merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. This implementation example illustrates the benefits of the proposed design methodology

Design methodology for dynamically reconfigurable systems

National audienceIn this paper we present an automatic design generation methodology for heterogeneous architectures composed of microprocessors, DSPs and FPGAs. This methodology is based on an adequation algorithm architecture where application is represented by a control data flow graph and architecture by an architecture graph. We focus on how to take into account specificities of partially reconfigurable components during the adequation process and for the design generation. We present a method which generates automatically the design for both fixed and partially reconfigurable parts of a FPGA. This method uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration and buffer merging to minimize memory requirements of the generated design

Méthodologie de conception haut niveau pour architectures reconfigurables dynamiquement

Nous présenterons dans cette thèse une méthodologie de conception pour les architectures reconfigurables dynamiquement. Cette méthodologie permet la spécification et la modélisation à un haut niveau de l architecture reconfigurable dynamiquement jusqu à la génération RTL du design pour implantation matérielle. Cette méthodologie est basée sur l utilisation du logiciel SynDEx qui permet une spécification haut niveau de l algorithme de l application ainsi que l architecture hétérogène composée de processeurs, DSP et FPGA. Une Adéquation Algorithme Architecture (AAA) est alors possible. Notre travail se focalise sur l introduction des architectures matérielles reconfigurables dynamiquement et notamment les dernières générations de FPGA partiellement reconfigurables dans ce flot de conception haut niveau. Nous abordons dans ce travail la prise en compte de la reconfiguration dynamique, la génération automatique de l architecture matérielle, la gestion des phases de reconfigurations dynamiques ainsi que l optimisation de celle-ci pour l architecture générée.This document presents a methodology flow targeting runtime reconfigurable components. This methodology is based on a high level specification of the dynamically reconfigurable architecture and handles RTL generation steps for implementation. This methodology uses SynDEx CAD software for algorithm specification at system level as well as heterogeneous architecture specification, composed of FPGAs and DSPs. A matching process (AAA) is proceed to find the best implementation of the application over the architecture. Our work is focused on the use of runtime reconfigurable components and specially lasts FPGA devices.RENNES-INSA (352382210) / SudocSudocFranceF

F.: Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation

Dynamic reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture process. We present a method which generates automatically the design for both partially and fixed parts of FPGAs. The runtime reconfiguration manager which monitors dynamic reconfigurations, uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration. We demonstrate the benefits of this approach through the design of a dynamic reconfigurable MC-CDMA transmitter implemented on a Xilinx Virtex2. 1